1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to the layout structure and write operation of write wirings to write data in memory cells.
2. Description of the Related Art
An MRAM (Magnetic Random Access Memory) is a device which stores information by using a magnetoresistive effect. Since an MRAM has nonvolatility, high-speed operation, high integration, and high reliability, MRAMs are expected as memory devices capable of replacing a DRAM (Dynamic Random Access Memory) or EEPROM (Electrically Erasable and Programmable Read Only Memory), and development of MRAMs is progressing.
In an MTJ (Magnetic Tunnel Junction) element used in a memory cell of an MRAM, an insulating film is sandwiched between two ferromagnetic films. The MTJ element has the tunneling magnetoresistive effect. That is, the magnitude of a tunneling current changes between a parallel state in which the magnetization directions of the two ferromagnetic materials are parallel to each other and an anti-parallel state in which the magnetization directions are anti-parallel. When the magnetization directions are parallel, the resistance of the MTJ element is small because the tunneling current is large. When the magnetization directions are anti-parallel, the resistance of the MTJ element is large because the tunneling current is small. An MRAM stores binary information by defining, as “0” data, the state in which the resistance of the MTJ element is small and defining, as “1” data, the state in which the resistance of the MTJ element is large.
Presently, there are many challenges in implementing a large-capacity MRAM. Especially, how to reduce the write current is the largest challenge. When the write current is reduced, the power consumption of the MRAM can be reduced. In addition, since the write driver can be reduced, the chip size, i.e., the chip manufacturing cost can also be reduced.
In a conventional general MRAM (e.g., IEEE Journal of Solid-State Circuits, Vol. 38, No. 5, May 2003, pp. 769–773, and Transactions of Symposium on VLSI Circuits, pp. 217–220), the write is executed by using the synthetic field of two write fields generated by write currents which are supplied to a bit line and a word line laid out perpendicularly to each other. The MTJ element is laid out such that its axis of easy magnetization is directed in the same direction as that of the word line. The synthetic field is generated in the 45° direction with respect to the MTJ element. Hence, when the write fields by the bit line and word line have the same magnitude, the synthetic field is √{square root over (2)} times.
Methods to reduce the write current can roughly be classified into a method of reducing the switching field of the MTJ element by improving the characteristics of the magnetoresistive element itself and a method of more efficiently applying the write field generated by the write current to the MTJ element. As the latter method, for example, a method of shortening the distance between the write wiring and the MTJ element, a method of concentrating the flux by adding a so-called yoke structure around the write wiring (e.g., U.S. Pat. No. 5,956,267), and a method of decreasing the relative angle between the write fields generated by the bit line current and word line current to smaller than 90° to make the synthetic field larger than before (e.g., U.S. Pat. No. 6,522,579 and Jpn. Pat. Appln. KOKAI Publication No. 2002-289807) have been proposed.
In U.S. Pat. No. 6,522,579, the word line is laid out linearly in the direction of axis of easy magnetization of the MTJ element. The bit line is laid out obliquely with respect to the word line. The relative angle between the write field due to the bit line current and the write field due to the word line current is decreased to 90° or less, thereby making the synthetic field larger than before. In this method, however, since the bit line is laid out obliquely, the layout of a bit line driving circuit and the like is complex. For this reason, it is difficult to lay out cell portions.
On the other hand, in Jpn. Pat. Appln. KOKAI Publication No. 2002-289807, the bit line is laid out linearly in the direction of axis of hard magnetization of the MTJ element. The word line is laid out perpendicularly to the bit line as a whole wiring but is bent at right angles near the MTJ element so that the word line is parallel to the bit line. The word line current flows the shortest route at the right-angled portion near the MTJ element. For this reason, near the MTJ element, the word line current flows obliquely with respect to the layout direction of the word line. With this arrangement, the relative angle between the write field by the bit line current and the write field by the word line current is decreased to 90° or less to make the synthetic field larger than before while maintaining the conventional layout in which the whole bit line and word line run perpendicularly to each other, like before. However, since the bit line is laid out perpendicularly to the direction of axis of easy magnetization of the MTJ element, the direction of synthetic field is not 45° with respect to the easy-axis direction of the MTJ element. The portion with the smallest switching field in the asteroid curve of the MTJ element cannot be used.